No need to wbinvd before HLT (entering C1) as the processor continues
to participate in the full cache coherency protocol in this sleep
state.
Signed-off-by: Keir Fraser <keir@xen.org>
if ( cx->entry_method == ACPI_CSTATE_EM_FFH )
{
/*
- * cache must be flashed as the last ops before cpu going into dead,
- * otherwise, cpu may dead with dirty data breaking cache coherency,
+ * Cache must be flushed as the last operation before sleeping.
+ * Otherwise, CPU may still hold dirty data, breaking cache coherency,
* leading to strange errors.
*/
wbinvd();
}
default_halt:
- wbinvd();
for ( ; ; )
halt();
}
static void default_dead_idle(void)
{
- /*
- * cache must be flashed as the last ops before cpu going into dead,
- * otherwise, cpu may dead with dirty data breaking cache coherency,
- * leading to strange errors.
- */
- wbinvd();
for ( ; ; )
halt();
}